Digital logic design software

Competency Group: Electrical Engineering

Type: Software Simulation Tool 

Description: VHDL, or VHSIC (Very High Speed Integrated Circuits) Hardware Description Language is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL is commonly used to write text models that describe a logic circuit. Such a model is processed by a synthesis program, only if it is part of the logic design. A simulation program is used to test the logic design using simulation models to represent the logic circuits that interface to the design. This collection of simulation models is commonly called a test bench. E.g. Will produce sequenced outputs of timing diagrams describing digital circuits.

Citation for Description: VHDL. (2012). Retrieved from Wikipedia,

Units: Usually in the form of a text file with all simulation parameters within.

Advantages: The key advantage of VHDL, when used for systems design, is that it allows the behavior of the required system to be described (modeled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires).

Limitations: Requires a good level of programming skills and can be difficult to interpret.

Regulations: IEEE Standards Association. (2012). 1076.3-1997 — IEEE Standard VHDL Synthesis Packages. Retrieved from

Target Audience: Engineering

Relevant to Universal Design: No

Stages and Steps: 3.5, 5, 6

Purchase Resource: Applied VHDL Course. (2007). Retrieved from

Purchase Resource: Bhasker, J. (1998). A VHDL Primer. Retrieved from